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In this talk, I present our recent research on using deep learning to automate chip designs with a focus on design creation. The problem is challenging as the deep learning agent to need come up with an optimized circuit microarchitecture, and the available training examples are very limited. Coupled with our multi-decade research high-level synthesis (HLS), we developed and integrated multiple deep learning techniques, such as hierarchical representation with graph-based neural networks (GNNs), active learning with cross-entropy minimization, cross-modality learning between GNNs and large language models, and hierarchical mixture of expert modeling. We achieved promising results on both HLS quality prediction and design space exploration for general applications. When coupled microarchitecture guided optimization for regular structures, such as systolic arrays and stencil computation, we show that it is possible to automate IC designs so that most software programmers can design their own chips for a wide range of applications for better performance and energy efficiency, which is much needed as we are approaching the end of Moore’s Law scaling.
Jason Cong is the Volgenau Chair for Engineering Excellence Professor at the UCLA Computer Science Department (and a former department chair), with joint appointment from the Electrical and Computer Engineering Department. He is the director of Center for Domain-Specific Computing (CDSC) and the director of VLSI Architecture, Synthesis, and Technology (VAST) Laboratory. Dr. Cong’s research interests include novel architectures and compilation for customizable computing, synthesis of VLSI circuits and systems, and quantum computing. He has over 500 publications in these areas, including 19 best paper awards, and 4 papers in the FPGA and Reconfigurable Computing Hall of Fame. He and his former students co-founded AutoESL, which developed the most widely used high-level synthesis tool for FPGAs (renamed to Vivado HLS and Vitis HLS after Xilinx’s acquisition). He is member of the National Academy of Engineering, the American Academy of Arts and Sciences, and a Fellow of ACM, IEEE, and the National Academy of Inventors. He is recipient of the SIA University Research Award, the EDAA Achievement Award, the IEEE Robert N. Noyce Medal for “fundamental contributions to electronic design automation and FPGA design methods”, and the Phil Kaufman Award for “sustained fundamental contributions FPGA design automation technology, from circuit to system levels, with widespread industrial impact”.
