Future AI Packaging Trends, Challenges and Thermo-Mechanical Considerations to Maximize Performance and Energy Efficiency

Abstract:

With the remorseless pace of LLM, generative and agentic AI model evolution, Advanced Packaging scaling is stressed like never before.  TSMC public roadmaps project the need for being ready with >7X reticle CoWoS integration by 2027 and even larger beyond.  CPO connectivity for scale out switches is an emerging trend, and future roadmaps would see a need in the scale up domain as well. Power delivery density is another challenging area as GPU compute devices are expected to push well beyond 2kW. 

With these trends, current packaging approaches to scaling 2.5D large integration sizes, assembling on ever larger substrates including photonic connectivity will be challenged and new approaches may need to be explored.  In this talk we will explore the challenges, future roadmap trends, and some key bottlenecks that need to be addressed.

Bio:

Dr. Suresh Ramalingam is currently VP for Disruptive Packaging Platforms, Office of CTO at Applied Materials.  Prior to Applied Materials he was a Corporate Fellow at AMD.  His career spans 32 years in Flip chip /Photonics/2.5D & 3D/CPO Packaging Development at Xilinx, AMD, Intel and others.  He is an IEEE Fellow for his leadership and technology innovation to commercialize 2.5D Silicon Interposer.  Dr. Ramalingam holds 140 patents, 50+ publications, SEMI and Ross Freeman Awards for Technical Innovation, ECTC and IMAPS Best Paper Awards and contributed a book chapter on 3D Integration in VLSI Circuits.  He graduated in 1994 with a Ph.D. in Chemical Engineering from Massachusetts Institute of Technology, Cambridge after completing his bachelor’s degree from Indian Institute of Technology, Chennai.