Gate-All-Around NanoSheet CMOS Technology

Abstract / Description: 

In recent years, Gate-All-Around (GAA) NanoSheet transistor emerged as the leading architecture to continue CMOS scaling beyond FinFET. This presentation will first discuss how NanoSheet CMOS technology meets the future requirements of both High-Performance-Compute (HPC) and Low-Power applications by providing the best Power-Performance-Area trade-off at the 3nm node and beyond. Fundamental concepts and advantages of the GAA NanoSheet architecture in the areas of device, process-integration and patterning will be reviewed. The second part will focus on recent progress in the art and present how GAA NanoSheet can deliver a sub-50nm Contacted Gate Poly-Pitch (CPP) technology with variable sheet width up to 70nm, improved gate length control, and novel Multi-Vt scheme for application tailoring. Further, key remaining challenges of Nanosheet device technology associated with the fabrication, scaling, and maturity for high volume manufacturing will be examined. Finally, recent hardware results showcasing the significant potential of GAA NanoSheet technology for cryogenic device applications will be reviewed.

Bio: 

Julien Frougier is a Senior Technology Development Engineer at IBM Research, where he focuses on the research and development of Advanced Logic CMOS Technology for High-Performance Computing (HPC) and Low-Power applications. He played a pivotal role in the development and qualification of Gate-All-Around (GAA) NanoSheet CMOS technology, enabling scaling beyond FinFET and contributing to the demonstration of the world’s first 2-nanometer chip technology in 2021.

He earned dual Master’s degrees in Material Science and Engineering from the Institut National des Sciences Appliquées and in Fundamental Physics from Université Paul Sabatier, France, in 2011. He completed his Ph.D. in Condensed Matter Physics at the Albert Fert Laboratory, France, in 2014. From 2015 to 2016, he was a Post-Doctoral Fellow at the Pennsylvania State University with research focused on the design, fabrication, and characterization of monolithic sub-kT/q Field Effect Transistors for energy-efficient computing applications.

He has co-authored over 40 peer-reviewed publications and international conference papers. He holds over 400 filed patents and is an IBM Master Inventor. His innovations and technical expertise have been recognized with 4 Outstanding Technical and Innovation Achievement Awards from IBM.