Si CMOS technology has dominated the microelectronics industry, with continued scaling. However, future scaling is reaching practical and fundamental limits. Currently, strained-Si channel with high-k/metal gate is the dominant technology. Si FinFETs have provided further innovation to improve electrostatic control of the channel and thus reduce leakage. However, performance enhancement of Si CMOS is beginning to saturate with scaling to nanoscale. To go beyond these limits novel materials and structures are being aggressively studied. A channel material with high carrier mobility can increase drive current and reduce power consumption and delay. Higher mobility semiconductors, like Ge, GeSn and III-Vs, together with innovative device structures may perform better than even very highly strained Si. III-Vs have opened totally new areas of applications, e.g., photonics, power, etc. Carbon nanotubes and graphene offer very high mobility, excellent electrostatic control of the channel but have problems in manufacturability. Graphene also has the problem of small bandgap making it not very useful for logic. Recently 2D materials like metal sulfides, telurides and selenides have emerged as potential candidates for nanoscale devices.
The scaling paradigm is also threatened by interconnect limits including excessive power dissipation, insufficient bandwidth, and signal latency for both off-chip and on-chip applications. Many of these obstacles stem from the physical limitation of Cu-based electrical wires, exacerbated by the increase in Cu resistivity, as wire dimensions and grain size become comparable to the bulk mean free path of electrons in Cu (~40nm). This makes it imperative to examine alternate interconnect schemes for future such as carbon nanotubes, optical interconnects and three-dimensional (3-D) integration.
Wide band gap semiconductor, such as gallium nitride, diamond and metal oxides provide solutions beyond silicon for power and High frequency electronics. Leveraging the wide bandgap materials defines the next generation electronics in these areas. It is important to understand these materials to better implement in the devices and assess the benefit through circuit and system applications.
Is Ge PMOS and III-V NMOS co-integration on Si feasible or a headache for the manufacturing folks? Can we have all Ge or all III-V CMOS or it is just a fantasy? Can CNT FETs become manufacturable? Are 2D materials more promising? Do the CNTs and graphene based interconnects offer significant advantage over Cu/low-k? Will optical interconnects be ever integrated on a chip? Is three-dimensional (3-D) integration technically and economically feasible? Will wide bandgap materials revolutionize power and high frequency electronics? This focus area will try to answer these questions.
Focus Area Leads
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Prof. Paul McIntyreMaterials Science and Engineering |
Prof. Srabanti ChowdhuryElectrical Engineering |
