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With basic Moore's Law scaling more or less stopping, innovation at the system level is necessary. But, it cannot be a simple replacement -- the success of SystemX initiatives will depend on accurate understanding of the strengths and weaknesses of the underlying future technology scaling. This talk will examine the landscape of Moore's Law (10nm, 7nm, 5nm) and identify strengths and weakness of the underlying scaling for the purpose of fueling conversations at the SystemX level.
Greg Yeric earned his BSEE, MSEE, and PhD in Microelectronics at The University of Texas at Austin, in 1987, 1989, and 1993, respectively. Dr. Yeric began his career at Motorola’s Advanced Products Research and Development Laboratories in the area of semiconductor process integration, subsequently working at TestChip Technologies, HPL Technologies, and Synopsys, all in the areas of test structures, technology development, and yield analysis. He is currently a Senior Principal R&D engineer atARM holdings, focusing on design-technology co-optimization and predictive technology. His recent invited talks span a wide variety of design-technology interactions, including the International Symposium on EUV Lithography, The International Conference on Microelectronic Test Structures, the International Test Conference, and the International Electron Devices meeting.
