The last decade has seen massive improvements in mobile compute performance, along with dramatic improvements in power efficiency. At Apple, custom SoC designs drive multiple product breakthroughs. The CPU inside the Apple A9 chip in iPhone 6s runs up to 70% faster and the GPU up to 90% faster than they did in the A8, delivering both desktop-class and console-class performance that you can hold in your hand. This has all been done without decreasing battery life. In this talk some of the unique technical challenges faced by mobile SoC designers will be discussed, along with some of the complex decisions that are considered when engineering silicon at Apple.
Jared Zerbe was born in New York City in 1965 & received his BSEE from Stanford University in 1987. After 5 years at VLSI Technology and MIPS computer systems, he joined Rambus Inc., where over 21 years he specialized in the design of high-speed I/O, PLL/DLL clock-recovery, and high-performance & low-power SerDes interfaces. While at Rambus, Jared was issued over 100 patents, taught courses at Berkeley and Stanford in high-speed I/O design, and authored/co-authored over 40 IEEE conference and journal papers. He also served on the program committee for VLSI Circuits and as an associate editor for the Journal of Solid State Circuits. In 2013, Jared joined Apple where he is currently a Silicon Systems Architect.
