Memory - the N3XT Frontier

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Memory - the N3XT Frontier
Thursday, February 25, 2016 - 4:30pm to 5:30pm
Allen, 101x Auditorium
Prof. H.-S. Philip Wong, Stanford University
Abstract / Description: 

The adoption of Flash in the memory hierarchy (albeit on a separate chip from the processor) inspired the exploration of computing architectures that capitalize on the salient features of Flash: non-volatility and high density. At the same time, new types of non-volatile memory have emerged that can easily be integrated on-chip with the microprocessor cores because they use a different set of materials and require different device fabrication technologies from Flash. Some of them can be programmed and read quickly; others can have very high data storage density. Importantly, all of these memories are free from the limitations of Flash — that is, low endurance, need for high voltage supply, slow write speed and cumbersome erase procedure. Coincidentally, these new memories store information using new types of physics that do not rely on storing charge on a capacitor as is the case for SRAM, DRAM and Flash

I will give an overview of the “new” memory technologies that are being explored currently in industry and in academia: spin-transfer torque magnetic memory, resistive switching metal oxide memory, conductive bridge memory, phase change memory. I will go over the fabrication process, essential device characteristics, and potential applications. To facilitate a connection with circuit designers, a compact model for RRAM has been developed and made available to the public. I will describe our efforts to explore device size scaling below 10 nm as well as 3D stacking of RRAM and the use of nanomaterials such as graphene in RRAM and PCM devices.


H.-S. Philip Wong is the Willard R. and Inez Kerr Bell Professor in the School of Engineering.  He joined Stanford University as Professor of Electrical Engineering in September, 2004. From 1988 to 2004, he was with the IBM T.J. Watson Research Center. At IBM, he held various positions from Research Staff Member to Manager, and Senior Manager. While he was Senior Manager, he had the responsibility of shaping and executing IBM’s strategy on nanoscale science and technology as well as exploratory silicon devices and semiconductor technology. His present research covers a broad range of topics including carbon electronics, 2D layered materials, wireless implantable biosensors, directed self-assembly, nanoelectromechanical relays, device modeling, brain-inspired computing, and non-volatile memory devices such as phase change memory, conductive bridge memory, and metal oxide resistance change memory. He is a Fellow of the IEEE. He served as the Editor-in-Chief of the IEEE Transactions on Nanotechnology in 2005 – 2006, sub-committee Chair of the ISSCC (2003 – 2004), General Chair of the IEDM (2007), and is currently the Chair of the IEEE Executive Committee of the Symposia of VLSI Technology and Circuits. He is the founding Faculty Co-Director of the Stanford SystemX Alliance – an industrial affiliate program focused on building systems.