Energy-Efficient Hardware for Embedded Vision and Deep Convolutional Neural Networks

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Energy-Efficient Hardware for Embedded Vision and Deep Convolutional Neural Networks
Monday, May 23, 2016 - 4:30pm to 5:30pm
Packard Building, Room 202
Prof. Vivienne Sze, MIT
Abstract / Description: 

Visual object detection and recognition are needed for a wide range of applications including robotics/drones, self-driving cars, smart Internet of Things, and portable/wearable electronics.  For many of these applications, local embedded processing is preferred due to privacy or latency concerns.  In this talk, we will describe how joint algorithm and hardware design can be used to reduce the energy consumption of object detection and recognition while delivering real-time and robust performance.  We will discuss several energy-efficient techniques that exploit sparsity, reduce data movement and storage costs, and show how they can be applied to popular forms of object detection and recognition, including those that use deep convolutional neural nets (CNNs).  We will present results from recently fabricated ASICs (including our deep CNN accelerator named “Eyeriss”) that demonstrate these techniques in real-time computer vision systems.


Vivienne Sze is an Assistant Professor at MIT in the Electrical Engineering and Computer Science Department.  Her research interests include energy-aware signal processing algorithms, and low-power circuit and system design for multimedia applications. Prior to joining MIT, she was a Member of Technical Staff in the R&D Center at TI, where she developed algorithms and hardware for the latest video coding standard H.265/HEVC.  She is a co-editor of the book entitled “High Efficiency Video Coding (HEVC): Algorithms and Architectures” (Springer, 2014).  

Dr. Sze received the B.A.Sc. degree from the University of Toronto in 2004, and the S.M. and Ph.D. degree from MIT in 2006 and 2010, respectively. In 2011, she was awarded the Jin-Au Kong Outstanding Doctoral Thesis Prize in electrical engineering at MIT for her thesis on “Parallel Algorithms and Architectures for Low Power Video Decoding”.  She is a recipient of the 2016 3M Non-tenured Faculty Award, the 2014 DARPA Young Faculty Award, the 2007 DAC/ISSCC Student Design Contest Award and a co-recipient of the 2008 A-SSCC Outstanding Design Award.