A focus on energy efficiency in the late CMOS design era, requires extra careful attention to system reliability and resilience to hardware-sourced errors. At the same time, the emergence of AI (cognitive) applications as a key growth segment is quite obvious. This talk will attempt to address the special challenges that next generation AI (or cognitive) systems pose, with a particular focus on next generation cognitive IoT architectures. We will discuss this primarily from the point of view of providing energy-efficient resilience in environments that are likely to have built-in vulnerability to errors. Such uncertainty stems not just from potentially error-prone (late CMOS) hardware designed for extreme efficiency, but also from algorithmic brittleness of the most prevalent forms of machine learning/deep learning (ML/DL) solution strategies today. In that context, we will briefly examine the promise of the Adaptive Swarm Intelligence (ASI) architectural paradigm that we have recently started investigating at IBM Research. This is a form of distributed or decentralized computing applied to the world of mobile cognitive IoT, backed by resilient support from back-end cloud (server) systems. In addition to examining the promises of inherent system architectural scalability and in-field, continuous learning that ASI offers, we will argue (albeit philosophically!) about why this could open the door to new models of self-aware systems that mimic cooperative and conscious problem solving in a human setting.
PRADIP BOSE is a Distinguished Research Staff Member and Manager of the Efficient & Resilient Systems Department at IBM T. J. Watson Research Center, Yorktown Heights, NY. He has been involved in the design and pre-silicon modeling of virtually all IBM POWER-series microprocessors, since the pioneering POWER1 (RS/6000) machine, which started as the Cheetah (and subsequently America) superscalar RISC project at IBM Research. From 1992-95, he was on assignment at IBM Austin, where he was the lead performance engineer in a high-end processor development project (POWER3). During 1989-90, Dr. Bose was on a sabbatical assignment as a Visiting Associate Professor at Indian Statistical Institute, India, where he worked on practical applications of knowledge-based systems. His current research interests are in high performance computers, power- and reliability-aware microprocessor architectures, pre-silicon modeling and validation. He is the author or co-author of over ninety refereed publications (including several book chapters) and he also serves as an Adjunct Professor ar Columbia University. He has received twenty eight Invention Plateau Awards, several Research Accomplishment and Outstanding Innovation Awards from IBM. He holds the title of IBM Master Inventor. Dr. Bose served as the Editor-in-Chief of IEEE Micro from 2003-2006 and as the chair of ACM SIGMICRO from 2011-2017. He is an IEEE Fellow and a member of the IBM Academy of Technology.
