Versal-ACAP Architecture, Programming, Machine Learning and 5G

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Versal-ACAP Architecture, Programming, Machine Learning and 5G
Thursday, April 30, 2020 - 4:30pm to 5:30pm
Zoom (Webinar)
Chris Dick - Xilinx
Abstract / Description: 

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This presentation will provide an overview of one of the new generation of 7nm devices from Xilinx, the Versal ACAP multi-core vector processor. The overall device architecture together with a detailed description of the Vector processor datapath will be presented. The programming model for the device will be described along with some application use cases for machine learning inference and 4G/5G wireless radio will be covered.


Chris is a Xilinx fellow and manages the machine learning applications team at Xilinx. His research and product development background is in the area of real-time signal processing with a particular emphasis on 4G and 5G wireless systems. During his tenure at Xilinx he initiated the Xilinx wireless baseband and radio R\&D programs. His current focus is on the Xilinx 7nm Versal ACAP VLIW multi-processor device. For the past 3 years he has been working in the area of machine learning with a particular emphasis on using the Versal architecture for machine learning inference workloads. He has over 200 publications, 70 patents and is an adjunct professor at Santa Clara University in Silicon Valley where he teaches a class on machine learning using FPGAs. Chris has been an advisor to the National Science Foundation in the area of Application-Specific Hardware/Software, and FPGA-based and Reconfigurable Systems, and has been an advisor to the US Defense Sciences Research Agency - an advisory arm of DARPA.