Cold CMOS for Hot Chips --Cryogenic Electronics for High Performance Computing

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Cold CMOS for Hot Chips --Cryogenic Electronics for High Performance Computing
Thursday, September 17, 2020 - 4:30pm to 5:30pm
Zoom (Webinar)
Jin Cai - TSMC
Abstract / Description: 

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CMOS scaling and its power-performance-density-cost benefits have been the driving force behind the semiconductor industry. I will first review CMOS evolution over the last half century with a focus on recent progress. Due to CMOS leakage current constraints, supply voltage reduction has been stalled for a while which makes energy efficiency gain more difficult. Major efforts were undertaken to search for low voltage switches such as tunnel FET, negative capacitance FET and non CMOS logic but practical implementation appears far away. For high performance computing applications, cryogenic operation provides a straightforward way to reduce supply voltage due to steepened subthreshold slope and sharp turn-off behavior. In this talk, I will discuss various benefits of cryogenic operation, some of them were recognized long ago but have not been discussed in the context of advanced CMOS technologies and some of them are not obvious. I will also highlight the stringent requirement on the energy efficiency of refrigerators for overall power benefit.


Jin Cai received his B.S. degree in physics from Fudan University in Shanghai, China and the M.S. and Ph.D. degrees in electrical engineering from University of Florida. He was a research staff member at IBM T. J. Watson Research Center from 2000 to 2015. He is currently a deputy technical director at TSMC’s Corporate Research organization. His technical interests span from CMOS device scaling to beyond CMOS devices. He has published over 70 journal and conference papers and received over 60 US patents. He is an IEEE senior member and served as an associate editor for IEEE Electron Device Letters. He is an avid runner in his spare time and a Boston marathon finisher.