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In 1965 Gordon Moore, co-founder of Fairchild Semiconductors and also Intel Corporation, predicted that the number of transistors per die would double every year until 1975 if specific actions were taken to eliminate any inflection points. This represents the first example of a long-term roadmap for semiconductors.
By 1975 data showed his predictions to be correct. He then predicted that the number of transistors would double every two years for the foreseeable future if appropriate actions were taken. Following Gordon Moore’s demonstrated success of the roadmap methodology, the National Technology Roadmap for Semiconductors (NTRS) was formed in 1991 in the US; the roadmap became international (ITRS) in 1998 to collectively address a major inflection point (i.e., the end of the planar MOS silicon gate process). Following the ITRS recommendations the semiconductor industry sequentially developed in a very timely fashion Strained Silicon, High-K/Metal-Gate and FinFET into manufacturing. Beginning with 2016 the scope of the roadmap was extended to also include System and Architecture as well as trends on Cryogenic Electronics and Quantum Information Processing. In the not-too-distant future 2D space in ICs will reach fundamental limits and fully utilization of the third dimension (3D) to increase “functionality density” has already started. Furthermore homogeneous and heterogeneous integration of multiple technologies is already in progress and will become the way of the future. New recommendations for actions to be taken in the next 15 years have been formulated and will be presented.
Dr. Gargini was born in Florence, Italy and received a doctorate in Electrical Engineering in 1970 and a doctorate in Physics in 1975. He was a researcher at Stanford University and at Fairchild Camera and Instrument in Palo Alto in the early 70s. Joined Intel in 1978, responsible for MPU technology (e.g., 80286 and the 80386). In 1985 he headed the first submicron team. He made the Flip Chip packaging technology manufacturable in mid-90s. In 1996, he became Director of Technology Strategy, Intel Fellow; responsible for worldwide consortia research from 1993 to 2012; member of Sematech, SRC, IMEC, EIDEC and SIA Boards, Chairman of the NRI. Dr. Gargini led the industry-wide conversion to 300mm wafers as Chairman of the I300I initiative From 1998 to 2015, Dr. Gargini was Chairman of the ITRS sponsored by the WSC.
Since 2016 he is the Chairman of the IRDS sponsored by IEEE. He is co-chairman of the EUVL Symposium.
Dr. Gargini is a member of the Leadership Team of the International Network Generations Roadmap (INGR), an IEEE initiative.
Inducted in the VLSI Research Hall of Fame in 2009, IEEE Fellow in 2009, I-JSAP Fellow in 2014 and IEEE Life-Fellow in 2020.
