Design Space for Chiplet IO

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Design Space for Chiplet IO
Thursday, October 13, 2022 - 4:30pm to 5:30pm
Shriram 104
Ken Chang - Cadence
Abstract / Description: 

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With the advent of Chiplet technology, there are proliferations of Chiplet IO technologies / standards available – OHBI, AIB, BoW, UCIe, 112G XSR, etc.   Unfortunately, there is no one size fit all solutions for all the applications.  The solutions depend a great deal on system requirement – aggregate bandwidth, power, area, shoreline bandwidth density, latency, and above all system cost, which dictates package options – traditional organic packages and advanced fine pitch packages like CoWoS, EMIB, etc.   This talk analyzes the tradeoff of these conflicting requirements and propose solutions for a few benchmark applications.   We believe the wide parallel IO with advanced fine pitch packages offers the lowest power, area, latency, and highest bandwidth density solution and therefore is suitable for HPC and HyperScalar solutions.  This, nevertheless is at the expense of high cost due to the packaging, which is also not generally available for small or medium size business.  While the ultra-high speed serial IO presents an attractive solution for traditional packages and backward compatible to off-chip applications, its non-zero bit errors require FEC and hence result in high latency that is not acceptable by latency sensitive applications like HPC, and thus only suitable for switch applications.  There exists a medium speed, coded parallel IO that works for conventional organic packages and does not require FEC and therefore provide low latency close to the wide parallel solution.  With the optimized speed, the bandwidth and bandwidth density is close to both extreme solutions.  We believe this can benefit most of the small and mid size business and can provide best time-to-market for majority of applications – HPC, HyperScalers, and high volume consumer applications .  We will present one such solution – 40Gb/s/pin with 6b/7b coding and achieves 1.5 pJ/bit, 500Gbps/mm, and  5.4ns latency in 7nm and 5nm technology.


Dr. Ken Chang received M.S. and Ph.D. degrees from Stanford University and the B.S. degree from National Taiwan University, all in Electrical Engineering.  From 1999 to 2010, he was with Rambus Inc. He led several projects, including 16- and 20-Gb/s low-power memory interfaces exploring various signaling techniques. From 2010 to 2019, he was with Xilinx, where he led the SerDes Technology Group, focused on developing multistandard SerDes IPs for field-programmable gate arrays (FPGAs), covering top line rates from 10, 28, 56, 112 Gb/s, all capable of long reach transmission. He is currently  with Cadence, where he led the Design IP R&D organization, including SerDes, Chiplet IO, and memory interfaces, as a corporate vice president.  He has authored or co-authored over 50 the IEEE conference/journal publications and holds over 50 U.S. patents in the high-speed link area. Dr. Chang had served on technical program committees for ISSCC, VLSI, and CICC. He is an IEEE fellow.