How and Why 2.5D and 3D Will Revolutionize Silicon Design

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How and Why 2.5D and 3D Will Revolutionize Silicon Design
Thursday, October 20, 2022 - 4:30pm to 5:30pm
Shriram 104
Sam Naffziger - AMD
Abstract / Description: 

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For decades, Moore’s Law has delivered the ability to integrate an exponentially increasing number of devices in the same silicon area at a roughly constant cost. This has enabled tremendous levels of integration, where the capabilities of computer systems that previously occupied entire rooms can now fit on a single integrated circuit. In recent times, the steady drum beat of Moore’s Law has started to slow down.  Whereas device density historically doubled every 18-24 months, the rate of recent silicon process advancements has declined.  While improvements in device scaling continue, albeit at a reduced pace, the industry is simultaneously observing increases in manufacturing costs.  In response, the industry is now seeing a trend toward reversing direction on the traditional march toward more integration.  Instead, multiple industry and academic groups are advocating that systems on chips (SoCs) be “disintegrated” into multiple smaller “chiplets.” This talk details the technology challenges that motivated AMD to use chiplets, the technical solutions we developed for our products, and how we expanded the use of chiplets from individual processors to multiple product families.  From this foundation we will look towards the future of chiplet and 3D architectures that will require multi-disciplinary innovation across package technology, silicon design, accelerators, and the software to exploit them.


Samuel Naffziger is AMD senior vice president, Corporate Fellow, and Product Technology Architect. Naffziger works across the company to optimize product technology choices and deployment with a continued focus on driving best practice power/performance/area methodology to maximize product competitiveness, efficiency, and cost.

Naffziger has been the lead innovator behind many of AMD’s low-power features and chiplet architecture. He has over 32 years of industry experience with a background in microprocessors and circuit design at Hewlett Packard, Intel and AMD.

Naffziger received a Bachelor of Science degree in Electrical Engineering from the California Institute of Technology (CalTech) and a Master of Science from Stanford. Naffziger holds more than 130 U.S. patents in the field and authored dozens of publications and presentations on processors, architecture and power management. He is an IEEE Fellow.