Scalable AI Architectures for Edge and Cloud

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Scalable AI Architectures for Edge and Cloud
Thursday, February 2, 2023 - 4:30pm to Friday, February 3, 2023 - 5:30pm
Gates B12
Ivo Bolsens - AMD
Abstract / Description: 

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The world of artificial intelligence and machine learning (AI/ML) is fragmented into different domains, split by training and inference, and cloud versus edge. 

Training normally takes place in the cloud where many high-powered servers, plenty of memory, hardware accelerators, and high-speed networking can be thrown at the workload. Scaling-out workloads typically results in communication bottlenecks which can be alleviated with novel compute architectures where part of the AI/ML workload and network functions such as collectives are handled in the network.

Inference workloads can also be performed in a data center, but increasingly, inference tasks are migrating to the edge because of latency, bandwidth and privacy reasons. Most edge inference devices cannot afford the silicon or the power consumption to perform all calculations using full-precision, floating-point data formats and require more efficient utilization of the compute HW.

AI/ML accelerator scalable architectures that support both full- and reduced-precision numerical formats break down the artificial boundary between training and inference, cloud, network and edge, and enable the deployment of the same standard and familiar software tools for a unified architecture. These efficient edge AI accelerators employ architectural innovations such as dataflow and on-chip broadcast networks that permit data fetched from external memory to be reused many times once brought on-chip, thus saving power and scaling performance. 

The availability of a unified scalable dataflow architecture for machine learning breaks down the wall between distinctive phases of training and inference and edge vs cloud.

The unified architecture ensures that compatible data formats are used and optimizations for data-formats such as sparsity representations don’t break between cloud and edge. A scalable, unified architecture and continual learning throughout the lifetime of a deployed application departs from today’s conventional training and inference practice that relies on CPUs and GPUs in the data center and specialized devices in the edge. Yet, this unified approach seems the most logical path if the industry wants to make large gains in performance, accuracy, and power efficiency as AI/ML becomes pervasive from edge to cloud. 


Ivo Bolsens is senior vice president and chief technology officer (CTO), for the Adaptive and Embedded Computing Group (AECG) at AMD. He oversees AECG’s advanced hardware and software technology development, including future architecture directions and software stacks to enable emerging opportunities in the fields of machine learning and high-performance computing for edge and cloud. Bolsens leads the corporate initiative to establish AMD’s pervasive AI ecosystem and he manages the Open Source Program Office to accelerate solutions for programming AMD silicon. His team is also driving the  university program to create a thriving, global ecosystem for AMD technology in academia. 

Bolsens joined AMD from Xilinx  in February 2022 as part of the  largest acquisition in semiconductor industry.  At Xilinx, he served as CTO in charge of the long-term technology strategy and advanced development activities for all software and hardware products.

Bolsens joined Xilinx in June 2001 as its CTO, from the Interuniversity Microelectronics Centre (IMEC), the largest  semiconductor research center based in Belgium, where he was vice president, Design of Information and Communication Systems, leading the R&D of digital signal processing systems (DSP) for  video applications and wireless communication terminals, as well as the development of compilers for DSP processors and system-on-chip (SOC) design software. During his tenure at IMEC, he and his team spun-out three successful startups in the field of SOC design tools and wireless systems. 

Bolsens serves on the advisory boards of IMEC, the Engineering Departments of San Jose State University and Santa Clara University, and the Department of Electrical Engineering and Computer Sciences at UC Berkeley. He is also a board member of EvoNexus, a startup technology incubator.
Bolsens holds a master’s in Electrical Engineering and a Ph.D. in Applied Science from the Catholic University of Leuven in Belgium.