Silicon Photonic Transceiver Design and Integration with Advanced Packaging

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Silicon Photonic Transceiver Design and Integration with Advanced Packaging
Thursday, February 9, 2023 - 4:30pm to 5:30pm
Gates B12
Yohan Frans - AMD
Abstract / Description: 

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In many fields and applications, there is an ongoing trend to have systems with distributed/disaggregated compute nodes. In-package silicon photonic provides a path to high bandwidth, low power, and long-reach interconnects required in such systems. In this talk, we will discuss the design of a multi-chip module (MCM) prototype of an in-package silicon photonic transceiver using dense wavelength division multiplexing (DWDM). The photonic components are implemented in a photonic die, and the electronics (serdes, driver, TIA) are implemented in a FinFET CMOS die. High-density integrated fan-out (InFO) and organic interposer are used to integrate these components.


Yohan Frans received B.S. degree in EE from Bandung Institute of Technology, Indonesia in 1995 and M.S. degree in EE from Stanford University, California in 2001. From 2001 to 2012, he was with Rambus Inc. where he worked on high-performance and low-power serial links and memory interfaces. From 2012 to 2022, he was with Xilinx Inc, San Jose, CA, leading the developments of high-speed electrical and optical transceivers. He is currently managing the Serdes Technology team at AMD. His interests include high-speed mixed-signal circuit design, serial link architecture, transmitter/receiver design, PLL/DLL, memory interfaces, and low-power circuit architectures. He has been a member of ISSCC Technical Program Committee since 2017 and is currently serving as Wireline Sub-committee Chair.