Learnings and Architectural Trends from Edge AI Chip Designs

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Learnings and Architectural Trends from Edge AI Chip Designs
Thursday, February 29, 2024 - 4:30pm to 5:30pm
Gates B12
Thierry Tambe - Stanford University
Abstract / Description: 

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The unabated pursuit for omniscient and omnipotent AI is levying hefty latency, memory, and energy taxes at all computing scales. In this context, my research is building a heterogeneity of solutions co-optimized across the compute stack to generate breakthrough advances in arithmetic performance for on-chip machine learning, and natural language processing in particular. My work developed several edge AI chips to validate these solutions. In this talk, I will be highlighting key learnings gleaned from my experience working on these domain-specific chip projects. The learnings are distilled into five categories: 1) number systems, 2) sparsity, 3) memory, 4) power management, and 5) chip design productivity. I will point out notable architectural trends and offer perspectives for next-generation VLSI systems in the age of generative AI.


Thierry Tambe is an incoming Assistant Professor in Electrical Engineering at Stanford University, starting in the 2024 Fall. He is currently a research scientist at NVIDIA. His research interests include domain-specific silicon systems, efficient number formats, and scalable heterogenous integration for emerging AI and compute/memory-intensive applications. Prior to debuting his doctoral studies, Thierry was an engineer at Intel where he worked on mixed-signal architectures for high-bandwidth memory and peripheral interfaces on Xeon HPC SoCs. He received a B.S. (2010), M.Eng. (2012) from Texas A&M University, and a PhD (2023) from Harvard University, all in Electrical Engineering. Thierry Tambe is a recipient of the Best Paper Award at the 2020 ACM/IEEE Design Automation Conference, a 2021 NVIDIA Graduate PhD Fellowship, and a 2022 IEEE SSCS Predoctoral Achievement Award.