System complexity continues to grow rapidly, with more complex silicon platforms, more software, more new models distributing data capture, storage and computation across thousands of heterogeneous nodes from sensors to cloud. Even more significantly, new issues in security, robustness, safety and scalability are triggering a rethinking of much of the design process, design languages, the nature of verification and the monumental tasks in composing diverse components into stable solutions.
This workshop focused on three themes, related to the scaling of computing to meet the opportunity:
- What new abstractions are needed to capture design intent in ways that lead to both more productive development and more efficient implementations?
- How do we extend verification to deal with the larger scale and diversity of the systems, while addressing the demand for better security, safety and reliability?
- As design teams construct, reuse, adapt and compose hardware and software elements, how will robust system assembly really work?
| Technical Program | |||
|---|---|---|---|
| 9:00 | Welcome | Rick Bahr/ Chris Rowen | |
| 9:15 | Keynote: Flash Organizations: Crowdsourcing Complex Work via Reconfigurable Organizational Structures | Prof. Melissa Valentine (Stanford) | Member Content: PDF |
| Session: Design Abstraction Chair: Chris Rowen |
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| 10:15 | The Stanford AHA Center: Making Hardware Design Fun Again | Prof. Pat Hanrahan (Stanford) | Member Content: PDF |
| 10:45 | Unleashing the full performance of the FPGA platform while abstracting the hardware details | Ivo Bolsens (Xilinx) | Member Content: PDF |
| 11:15 | QED and Symbolic QED: Dramatic Improvements in SoC Pre-silicon and Post-silicon Validation | Prof. Subhasish Mitra (Stanford) | Member Content: PDF |
| Session: Design Verification Chair: Dr. Pat Hanrahan |
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| 1:00 | Sharply Reducing Custom IC Design Costs: The DARPA CRAFT Program |
Linton Salmon (DARPA) |
Member Content: PDF |
| 1:30 | Formal Verification of Neural Networks | Prof. Clark Barrett (Stanford) |
Member Content: PDF |
| 2:00 | System Synthesis: Challenges in automating system level design, verification and implementation | Serge Leef (Mentor) | Member Content: PDF |
| Session: System Assembly Chair: Rick Bahr |
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| 3:00 | Improving Analog Layout Productivity Using Digital Place & Route | Prof. Boris Murmann (Stanford) | Member Content: PDF |
| 3:30 | Innovation in the IoT Product Development Process | Moe Tanabian (Samsung) | Member Content: PDF |
| 4:00 | Tools for Driver Generation and Rapid HW/SW Development | Steven Bell (Stanford/Nvidia) | Member Content: PDF |
| 4:45 |
Panel: Where will we get the best leverage on productivity? |
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