Collaborative efforts of researchers at Stanford, University of California Berkeley, University of Michigan, and Carnegie Mellon University are working toward creating a faster and more efficient computing architecture.
The team describes their approach as 'N3XT, Nano-Engineered Computing Systems Technology.' N3XT will eliminate bottlenecks by integrating processors and memory like floors in a skyscraper and by connecting these components with millions of "vias," which play the role of tiny electronic elevators.
The key is the use of non-silicon materials that can be fabricated at much lower temperatures than silicon, so that processors can be built on top of memory without the new layer damaging the layer below.
N3XT high-rise chips are based on carbon nanotube transistors (CNTs). Transistors are fundamental units of a computer processor, the tiny on-off switches that create digital zeroes and ones. CNTs are faster and more energy-efficient than silicon processors. Moreover, in the N3XT architecture, they can be fabricated and placed over and below other layers of memory.
Mitra and Wong have already demonstrated a working prototype of a high-rise chip. At the International Electron Devices Meeting in December 2014 they unveiled a four-layered chip made up of two layers of RRAM memory sandwiched between two layers of CNTs.
In their N3XT paper they ran simulations showing how their high-rise approach was a thousand times more efficient in carrying out many important and highly demanding industrial software applications.
"When you combine higher speed with lower energy use, N3XT systems outperform conventional approaches by a factor of a thousand," Wong said.
Excerpts from the Stanford Report.
